Even though it may seem there is not much new under the ATE sun, all is not vanity.
I am writing this after having just attended the Advantest VOICE conference. This year was the 10th anniversary of VOICE. The conference was started 10 years ago as a forum for Verigy (now Advantest) ATE users to network, collaborate and share technical solutions. Teradyne has a similar annual TUG (Teradyne users group) conference.
As expected, there were a lot of "then" and "now" references during the welcome and keynote messages by Doug Lefever, CEO of Advantest America, and Michael Campbell, Senior VP of Engineering at Qualcomm, respectively. Certainly, the end markets identified by the foregoing speakers and other presenters as the key drivers for ATE - cloud apps, smart phones, system level test, automotive, and IOT - have changed in the past decade. However, the ATE value proposition precipitated by those key drivers does not appear to have changed much. Even Mr. Campbell seems to agree. He effectively said at one point in his talk that we don't care what the IOT endpoint does, we just need to know how to test the microprocessor, wireless transceiver, and other components comprising the endpoint module.
Another clue to the foregoing conclusion is that the roadmap presentations shown looked eerily the same as the overly detailed and largely unreadable presentations I created 10 years ago. As I did back then, these presentations promised lower cost-of-test and faster time-to-market for all who would join their camp. While lowering cost and improving time-to-market are still important, some of the common approaches to providing such value - higher density channels, parallel and/or concurrent test, multi-purpose instrumentation, and others - could be reaching certain limits after more than 10 years.
Even though it may seem there is not much new under the ATE sun, all is not vanity. We in the semiconductor test industry are instead tasked to discover new and innovative ways to increase the value provided by test. For example, along with the now obligatory higher density instrument introduction, I was definitely pleased to see at VOICE this year such innovative efforts as open-sourced test IP integration software, subscription-based test IP downloadable from the cloud (with free desktop test hardware), and various system-level test solutions.
We in the semiconductor test industry are tasked to discover new and innovative ways to increase the value provided by test.
More sophisticated test capacity planning is another relatively unexplored area that can offer a new approach to lowering cost-of-test and even improving time-to-market. As it has always been under the ATE sun, about half of the cost to test a given device is still attributable to the capital cost of the underlying test cell equipment. As equipment utilization is improved, so is the cost-of-test. Planning your test capacity with more accuracy (e.g., responsive to dynamic device forecasts) and more precision (e.g., down to the board, channel, and license levels) can effectively provide a new cost-of-test reduction mechanism rarely used. A good solution for providing test capacity management techniques will also facilitate test capacity planning collaboration across the test ecosystem, further improving time-to-market.
Delivering to the semiconductor industry such untapped test capacity planning improvements is our passion at Chip Nexus.