Test Assembly & Packaging Markets—West Hall, Level 1
Thursday, July 17, 2008
11:00am – 1:30pm
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On the Test Floor |
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Testing challenges continue to arise at both Wafer sort and Final test. A great many of these challenges have arisen from new materials (copper, low-K, etc.), shrinking die and the associated compression of pad pitches as well as tester to device under test (DUT) connectivity. The strategy for addressing these challenges is the subject of this session. |
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11:00am – 11:20am |
Planes, Test, and Capacity
Management
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